Modern computers and telecommunications systems provide great benefits including the ability to communicate information around the world. Conventional architectures for computers and telecommunications equipment include a large number of discrete circuits, which causes inefficiencies in both the processing capabilities and the communication speed.
For example, FIG. 1 illustrates such a conventional line card employing a number of discrete chips and technologies. In FIG. 1, conventional line card 100 includes the following discrete components: Classification 102, Traffic Manager 104, Buffer Memory 106, Security Co-Processor 108, Transmission Control Protocol (TCP)/Internet Protocol (IP) Offload Engine 110, L3+ Co-Processor 112, Physical Layer Device (PHY) 114, Media Access Control (MAC) 116, Packet Forwarding Engine 118, Fabric Interface Chip 120, Control Processor 122, Dynamic Random-Access Memory (DRAM) 124, Access Control List (ACL) Ternary Content-Addressable Memory (TCAM) 126, and Multiprotocol Label Switching (MPLS) Static Random-Access Memory (SRAM) 128. The card further includes Switch Fabric 130, which may connect with other cards and/or data.
Advances in processors and other components have improved the ability of telecommunications equipment to process, manipulate, store, retrieve and deliver information. Recently, engineers have begun to combine functions into integrated circuits to reduce the overall number of discrete integrated circuits, while still performing the required functions at equal or better levels of performance. This combination has been spurred by the ability to increase the number of transistors on a chip with new technology and the desire to reduce costs. Some of these combined integrated circuits have become so highly functional that they are often referred to as a System on a Chip (SoC). However, combining circuits and systems on a chip can become very complex and pose a number of engineering challenges. For example, hardware engineers want to ensure flexibility for future designs and software engineers want to ensure that their software will run on the chip and future designs as well.
The demand for sophisticated new networking and communications applications continues to grow in advanced switching and routing. In addition, solutions such as content-aware networking, highly integrated security, and new forms of storage management are beginning to migrate into flexible multi-service systems. Enabling technologies for these and other next generation solutions must provide intelligence and high performance with the flexibility for rapid adaptation to new protocols and services.
In order to take advantage of such high performance networking and data processing capability, it is important that such systems be capable of communicating with a variety of high bandwidth peripheral devices, preferably using a standardized, high-bandwidth bus. Although many proprietary high-bandwidth buses are possible, using a standardized bus allows the system to interface with a broader variety of peripherals, and thus enhances the overall value and utility of the system.
One high-bandwidth standardized bus that has become popular in recent years is the PCI Express (PCI-E or PCIe) interface. The PCIe interface, originally proposed by Intel as a replacement for the very popular but bandwidth limited personal computer PCI interface, is both high bandwidth and, due to the fact that it has now become a standard component on personal computer motherboards, very widely adopted. Hundreds or thousands of different peripherals are now available that work with the PCIe interface, making this interface particularly useful for the present advanced processing system.
In contrast to the earlier, parallel, PCI system, which encountered bandwidth limitations due to problems with keeping the large number of parallel circuit lines in synchronization with each other at high clock speeds, the PCIe system is a very fast serial system. Serial systems use only a very small limited number of circuit lines, typically two to transmit and two to receive, and this simpler scheme holds up better at high clock speeds and high data rates. PCIe further increases bandwidth by allowing for multiple serial circuits. Depending upon the PCIe configuration, there can be as few as 1 bidirectional circuit, or as many as 32 bidirectional serial circuits.
Although, on a hardware level, the serial PCIe system is radically different from the earlier parallel PCI system, the earlier PCI system was extremely successful, and the computer industry had made a massive investment in earlier generation PCI hardware and software. To help make the much higher bandwidth PCIe system compatible with the preexisting PCI hardware and software infrastructure, PCIe was designed to mimic much of the earlier parallel PCI data transport conventions. Earlier generation software thus can continue to address PCIe devices as if they were PCI devices, and the PCIe circuitry transforms the PCI data send and receive requests into serial PCIe data packets, transmits or receives these data packets, and then reassembles the serial PCIe data packets back into a format that can be processed by software (and hardware) originally designed for the PCI format. The PCIe design intention of maintaining backward compatibility, while providing much higher bandwidth, has been successful and PCIe has now become a widely used computer industry standard.
Although other workers, such as Stufflebeam (U.S. Pat. No. 7,058,738) have looked at certain issues regarding interfacing multiple CPUs to multiple I/O devices through a single switch (such as a PCIe switch), this previous work has focused on less complex and typically lower-performance multiple CPU configurations, that do not have to contend with the issues that result when multiple cores must coordinate their activity via other high-speed (and often on-chip) communication rings and interconnects.
Consequently, what is needed is an advanced processor that can take advantage of the new technologies while also providing high performance functionality. Additionally, this technology would be especially helpful it included flexible modification ability, such as the ability to interface with multiple high-bandwidth peripheral devices, using high-bandwidth star topology buses such as the PCIe bus.